library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity icy_light is
    port(pul, rst:in std_logic;
         led:out std_logic_vector(5 downto 0));
end icy_light;

architecture behav of icy_light is
signal i:std_logic_vector(2 downto 0);
begin
    process(pul, rst)
    begin
        if(rst = '0') then
            led <= "000000"; i <= "000";
        elsif(pul'event and pul = '1') then
            if(i = 5) then
                i <= "000";
            else
                i <= i + '1';
            end if;
            case i is
                when "000" => led <= "111110";
                when "001" => led <= "111101";
                when "010" => led <= "111011";
                when "011" => led <= "110111";
                when "100" => led <= "110111";
                when others => led <= "011111";
            end case;
        end if;
    end process;
end behav;